1. Field of the Invention
The invention relates to a method of plasma etching polysilicon with HBr and apparatus for improving plasma etching uniformity.
2. Description of the Related Art
Plasma processing systems wherein an antenna coupled to a radiofrequency (RF) source energizes gas into a plasma state within a process chamber are disclosed in U.S. Pat. Nos. 4,948,458; 5,198,718; 5,241,245; 5,304,279; 5,401,350; and 5,571,366. In such systems, the antenna is located outside the process chamber and the RF energy is supplied into the chamber through a dielectric wall or window. Such processing systems can be used for a variety of semiconductor processing applications such as etching, deposition, resist stripping, etc. When such systems are used for plasma etching a batch of consecutively processed semiconductor substrates, the etching rate and/or uniformity may change during the course of etching the batch of substrates. Such variation in etch rate/uniformity is undesirable since the features etched into the substrate may fall outside acceptable product parameters.
Polysilicon etching techniques are disclosed in U.S. Pat. Nos. 5,242,536; 5,314,573; 5,336,365; 5,368,684; and 5,763,327. Of these, the ""536 patent discloses anisotropic polysilicon etching in a parallel plate plasma etcher using HBr gas along with Cl2 and He. The ""573 patent discloses anisotropic polysilicon etching in a parallel plate plasma etcher using HBr gas along with HCI or Cl2. The ""365 patent discloses anisotropic polysilicon etching in an electron cyclotron resonance (ECR) plasma etcher using HBr gas along with Cl2 in a first step and HBr and He in a second step. The ""684 patent discloses anisotropic polysilicon etching in a magnetron plasma etcher using HBr gas, a mixture of HBr and Cl2 or a mixture of HBr and HCl. The ""327 patent discloses polysilicon etching in a plasma etcher using Cl2, Br2 or HBr, He and O2. 
Techniques for etching polysilicon using HBr alone or in combination with other gasses are described in U.S. Pat. Nos. 5,160,407; 5,180,464; 5,560,804; 5,591,664; 5,665,203; 5,670,018; 5,792,692; 5,801,077; 5,804,489; 5,861,343; 5,932,115; and 5,994,234.
U.S. Pat. No. 6,022,809 discloses a composite shadow ring used in a plasma etch chamber, the ring including an insert which does not generate contaminating oxygen gas when bombarded by a gas plasma such as a fluorine-containing plasma. The shadow ring is movably mounted in the bottom of a vacuum chamber such that a wafer can be loaded onto or off of an electrostatic chuck and plasma is generated in the chamber by a coil antenna surrounding a sidewall of the chamber. The shadow ring includes an outer body portion of silicon dioxide and an inner ring-shaped insert portion of silicon. During via etching of a spin-on-glass (SOG) layer the insert is intended to reduce generation of oxygen gas which can inhibit or attack polymeric sidewall passivation layers in the via openings thereby reducing tungsten plug loss near the peripheral edge of the wafer.
While there have been proposals in the prior art to improve polysilicon etch processes and while attempts have been made to prevent generation of oxygen during etching by use of pure silicon materials, there is a need in the art for improvements in etching uniformity of polysilicon.
The invention provides a method of consecutively processing a series of semiconductor substrates with minimal plasma etch rate variation following cleaning with fluorine-containing gas and/or seasoning of the plasma etch chamber. The method includes steps of (a) placing a semiconductor substrate on a substrate support in a plasma etching chamber, (b) maintaining a vacuum in the chamber, (c) processing the substrate by supplying an HBr-containing etching gas to the chamber and energizing the etching gas to form a plasma in the chamber, (d) removing the substrate from the chamber; and (e) consecutively processing additional substrates in the chamber by repeating steps (a-d), the etching step being carried out by maintaining a recombination rate of H and Br on a member surrounding the substrate at a rate sufficient to offset a rate at which Br is consumed across the substrate.
According to a preferred feature of the invention, the semiconductor substrate can include a layer of polysilicon which is etched with HBr during step (c) and/or the chamber is maintained at a vacuum pressure of less than 100 mTorr during step (c). During step (c) an RF bias of no more than 500 watts can be applied to the substrate by the substrate support.
In the preferred embodiment, the etching gas is energized into a plasma state by a planar or non-planar antenna separated from the interior of the chamber by a dielectric member. Preferably, the dielectric member is at least coextensive with the substrate support and the etching gas is supplied to the chamber by at least one gas inlet in the dielectric member.